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UVW Encoder Output IP

Block Info

doc_block_uvw_encoder.png
Version: 1.0
First Release: FPGAWB 2019.3-3

The UVW Encoder IP module generates UVW pulses using 3 equidistant sensors.

Examples

Example 1

The U, V, and W signals from the UVW Encoder Output block is connected to three Digital Output Blocks.

uvw_encoder_example.png