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Register Write IP

Block Info

doc_block_register_write.png
Version: 1.0
First Release: FPGAWB 2020.2-0

Examples

Example 1

The LVDT/RVDT Tx block gets the normalized angle input from the Wavegen 0. Wavegen 1 generates the Excitation signal when the LVDT/RVDT Tx runs in External excitation mode. The Register Write block in this example is used to append 16 bit of zeros(Constant) to the Wavegen 0 input.

register_write_example.png